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Bonhill Partners
London, UNITED KINGDOM
(on-site)
Posted
2 days ago
Bonhill Partners
London, UNITED KINGDOM
(on-site)
Job Function
Financial Services
Low-Latency C++ Engineer - Systematic Trading
The insights provided are generated by AI and may contain inaccuracies. Please independently verify any critical information before relying on it.
Low-Latency C++ Engineer - Systematic Trading
The insights provided are generated by AI and may contain inaccuracies. Please independently verify any critical information before relying on it.
Description
Low-Latency C++ Engineer - Systematic TradingWe're looking for a seasoned low-latency engineer to help push the boundaries of speed and efficiency across our trading systems. You'll be working at the intersection of software and hardware - tuning every layer of our stack, from the Linux kernel to our custom C++ frameworks, ensuring our trading infrastructure runs at nanosecond precision.
This is a hands-on, performance-driven engineering role within a team that obsesses over every CPU cycle, cache miss, and network packet.
What You'll Do
- Architect, implement, and refine ultra-low-latency C++ systems for execution, market data processing, and internal infrastructure.
- Analyze and optimize performance across compute, memory, cache, and networking layers using advanced profiling and benchmarking tools.
- Collaborate with FPGA, hardware, and network engineering teams to design holistic, cross-stack optimizations.
- Continuously improve our real-time telemetry, logging, and monitoring systems to surface microsecond-level insights.
- Experiment with kernel tuning, driver parameters, and CPU isolation to squeeze out every bit of performance.
What We're Looking For
- 5+ years of hands-on experience building and optimizing latency-sensitive C++ systems (C++17/20 preferred).
- Strong understanding of modern CPU architecture, instruction pipelines, NUMA, cache coherency, and memory management.
- Deep expertise with Linux internals - from kernel configuration and interrupt handling to low-level performance profiling (perf, eBPF, ftrace, etc.).
- Experience with lock-free data structures, high-performance networking (TCP/UDP/multicast), and concurrency models.
- Familiarity with RDMA, DPDK, or other kernel-bypass networking stacks is a plus.
- Comfortable working closely with FPGA, infrastructure, and research teams to optimize full-stack latency.
- A scientific mindset - you measure, test, and iterate to drive measurable latency gains.
We look forward to hearing from you!
Job ID: 81576477
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